1. Field of the Invention
The present invention relates to a semiconductor device and a method for forming the same. More particularly, the present invention relates to a thin film transistor applicable to liquid crystal electro-optical devices, contact type image sensors, and the like.
2. Description of the Prior Art
Insulated gate field effect semiconductor devices known to the present have been widely applied to various fields. Such semiconductor devices comprise a silicon substrate having integrated thereon a plurality of semiconductor elements so that the devices may function as integrated circuits (ICs) and large scale integrated circuits (LSIs).
In addition to the insulated gate field effect semiconductor devices of the type mentioned above, there is another type of such insulated gate field effect semiconductor devices which comprises a thin film semiconductor formed on an insulator substrate, rather than a silicon substrate. Those thin film insulated gate field effect semiconductor devices (referred to hereinafter as TFTs) are now more positively used, for example, in liquid crystal electro-optical devices as switching elements of pixels and driver circuits, and in read-out circuits of contact type image sensors and the like.
Those TFTs are produced, as mentioned above, by laminating thin films on an insulator substrate by a vapor phase process. This process can be conducted in an atmosphere controlled to a temperature as low as about 500xc2x0 C., or even lower. Moreover, low cost substrates such those made of soda-lime glass and borosilicate glass can be utilized in those TFTs. Thus, the insulated gate field effect semiconductor device of the latter type are advantageous in that they can be fabricated using low cost substrates, and that they can be readily scaled up by depositing the thin films on a substrate having a larger area with the only limiting factor being the dimension of the apparatus in which the thin films are vapor-phase deposited. Accordingly, application of such insulated gate field effect semiconductor devices to liquid crystal electro-optical devices having a large pixel matrix structure or to a one- or two-dimensional image sensors has been expected, and, in fact, a part of such expectations has been met already.
A representative structure for the latter type of TFTs is shown schematically in FIGS. 2 and 6.
Referring to FIG. 2, a typical structure of a conventionally known TFT is explained. In FIG. 2, a thin film semiconductor 2 made of an amorphous semiconductor is deposited on a glass insulator substrate 1, and the thin film 2 comprises on the surface thereof a source area and a drain area 3, source and drain contacts 7, and a gate 11.
Those types of TFTs comprise, as mentioned above, semiconductor layers having deposited by a vapor deposition process. Since the electron and hole mobilities of the semiconductor layers in those TFTs are significantly low as compared with those of the conventional ICs and LSIs, it has been customary to subject the semiconductor layer 2 to a heat treatment for the crystallization thereof.
In a conventional TFT as shown in FIG. 2, the gate 11 is covered with a relatively thick interlayer insulator film 4 such as a silicon nitride film and a silicon oxide film, and to this interlayer insulator film are provided contact holes by a photolithographic process. The source and drain contacts 7 are electrically connected with source and drain areas 3. If feeding points to the source and the drain were to be provided at such positions, the distance L between each of the feeding points and the channel end becomes considerably long.
As mentioned earlier, the TFTs fabricated by a thin film deposition process at low temperatures are significantly low in the carrier mobility. Even upon doping an impurity, the still low conductivity produces a resistance within this distance L. Accordingly, the conventional TFTs suffer poor frequency characteristics and increase in ON circuit, resistance. Furthermore, the area necessary for a TFT increases inevitably with increasing length of L. This made it difficult to accommodate a predetermined number of TFTs within a substrate of a limited dimension.
In FIG. 6, a thin film semiconductor 102 composed of an amorphous semiconductor is deposited on a glass insulator substrate 101, and the thin film 102 comprises on the surface thereof a source and a drain area 103, source and drain electrodes 107, and a gate 111.
The TFTs of this type in general are produced by first depositing a semiconductor film on the substrate, and, by patterning, forming island-like semiconductor areas 102 on the desired parts using a first mask. Then, an insulating film and further thereon a gate material are formed, from which a gate electrode 111 and a gate insulating film 106 are obtained by patterning using a second mask. A source and a drain area 103 are established on the semiconductor areas 102 in a self-aligned manner, using the gate electrode 111 and a photoresist formed using a third mask as masks. An interlayer insulator film 104 is formed thereafter. To this interlayer insulator film are provided contact holes using a fourth mask, so that the contacts may be connected to the source and the drain through those contact holes. A contact material is provided to the resulting structure thereafter, which is patterned to form contacts 107 using a fifth mask. Thus is obtained a complete TFT.
As can be seen from the foregoing description, a TFT in general requires five masks to complete a structure, and in a complementary TFT, six masks are necessary. Naturally, a more complicated IC should incorporate further more masks. The use of increased number of masks involves a complicated process for fabricating a TFT element, which accompanies frequent mask alignment steps. Such a complicated process inevitably results in a lowered yield and productivity of the TFT elements. The demand for larger electronic devices using the TFT elements, for making the TFT elements themselves more compact, and for finer patterning, makes the yield and productivity even worse. Thus, it has been desired to develop a simpler process which involves no complicated steps, and a TFT based on a novel structure which requires less masks.
An object of the present invention is to provide a semiconductor device based on a novel structure.
Another object of the present invention is to provide an insulated gate field effect semiconductor device having each of the feeding points for source and drain in proximity to the channel region at a shorter distance to the channel ends.
Still another object of the present invention is to provide a method for forming semiconductor devices using less masks.
The insulated gate field effect semiconductor device according to the present invention is characterized by that the TFT comprises a metal gate electrode having at least to the side thereof a film of an anodically oxidized gate electrode material. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact hole for the extracting contacts of the source and drain semiconductor regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate electrode.
To improve the carrier mobility in the semiconductor layer of the insulated gate field effect semiconductor device according to the present invention, if necessary, the substrate having deposited thereon a silicon semiconductor film containing hydrogen therein may be subjected to thermal treatment to thereby modify said semiconductor film into such having a crystalline structure. Furthermore, to minimize the distance L between the feeding points and the channel ends, a metal gate electrode may be provided, e.g., an aluminum gate electrode, and the outer (peripheral portion) of this gate electrode may be oxidized then to form at least on the side thereof a metal oxide film, e.g., an aluminum oxide film.
Furthermore, the gate electrode together with the aluminum oxide film surrounding said gate electrode may be used as a mask to form contact holes for the extract contacts of the source and the drain with a side surface of the contact hole located substantially on a side surface of the aluminum oxide film in a self-aligned manner. The present invention provides, as is shown in the schematic cross sectional view of FIG. 1, a TFT comprising a metal gate electrode 8 having at least on the side thereof an oxide layer 10 comprising the metal, e.g. an aluminum oxide layer, to which source and drain electrodes 7 (contacts for a drain and a source) connected to the source and drain semiconductor regions respectively are provided approximately at the end of the oxide layer. The source and drain electrodes 7 are connected to the source and drain semiconductor regions 3. By taking such a construction, a shorter distance L between said feeding points and the channels has been achieved. In FIG. 1, a channel is located adjacent to the gate electrode 8 between the source and drain semiconductor regions 3 under a gate insulating film 8. In FIG. 1, the gate insulating film 6 is provided between the channel and the gate electrode 8. In FIG. 1, a side of at least one of the source and drain electrodes 7 is substantially aligned with a side of the oxide layer 10. In FIG. 1, the oxide layer is in contact with the gate electrode and at least one of the source and drain electrodes. In FIG. 1, a side of the source semiconductor region is aligned with a side of the oxide layer and also a side of the drain semiconductor region is aligned with a side of the oxide layer.
Ideally, it is favorable to reduce the distance L to zero from the viewpoint of lowering the resistance (in FIG. 1, indeed, the distance L is approximately zero). However, difficulties ascribed to process technology, for example, a small extension of the source and the drain semiconductor regions under the gate, hinder achievement of a complete zero. Nevertheless, a shorter distance L still promises a considerable effect in reducing the resistance.
In the embodiment exemplified by FIG. 1, the aluminum oxide film around the gate electrode is established over the side and the upper plane of the gate electrode, i.e., over the whole outer plane exposed to the outside. However, the aluminum oxide film according to the present invention not necessarily be provided to the whole outer surrounding. The aluminum oxide film should be provided at least to cover the side of the gate electrode to shorten the distance L. If the aluminum oxide film is provided to the whole outer as is shown in FIG. 1, this film can be used as it is as a part of a mask at the fabrication of the contact holes, because the aluminum oxide film is hardly etched. Furthermore, other wiring, e.g., a wiring for the source electrode, may be crossed over this aluminum oxide film to establish a three-dimensional wiring which facilitates the later process steps for integration.
In the insulated gate field effect semiconductor device according to the present invention, what is meant by providing the contact holes for the extract contacts of the source and the drain in an approximately the same position as that of the ends of the gate electrode and the aluminum oxide film, is a structure resulting upon formation of contact holes in a self-aligned manner using the ends of the gate electrode and the aluminum oxide film, as well as a structure having a slight positional deviation in the case of using masks at the positioning, ascribed to the incomplete alignment of the masks. Referring to FIG. 1, for example, the edge portion of the insulator film 9 is sometimes displaced from the end of the aluminum oxide at the mask alignment when the contact portion alone is intended to form. Such a case is included in the latter case mentioned hereinbefore. In the former case taking advantage of the aluminum oxide film as a mask, i.e., in the case of extending the etching area of the insulator film up to the gate, the insulator film 9 can be completely removed from the gate, and the end of the source or the drain is certainly aligned with that of the aluminum oxide film 10 to result in a shortened distance L.
The aluminum oxide may be provided around the gate-electrode by anodically oxidizing said gate electrode. The anodic oxidation process comprises applying an electric current to a metal gate electrode having dipped in an acidic solution to oxidize the surface thereof by an electrochemical reaction. There may be used other processes, provided that the oxide film has a dense structure and that the oxidation can be effected rapidly.
The insulated gate field effect semiconductor device according to the present invention is also characterized by that it comprises a TFT gate electrode surrounded by an anodically oxidized film of the same material constituting the gate electrode, with the contacts (source and drain electrodes) connected to the source and the drain being brought into contact with the upper planes and the sides of the source and the drain each, and that said contacts (source and drain electrodes) being connected to each of the drain and the source extend on the upper surface of the oxidized film having provided surrounding said gate electrode.
As shown in the schematically shown cross sectional view of FIG. 5, the TFT according to the present invention comprises an anodically oxidized film 110 at least as the surroundings of the gate electrode 108 comprising a metal, with the upper planes and the sides of the source and drain semiconductor regions slightly sticking out from the ends of said anodically oxidized film. The source and drain semiconductor regions are connected to the contacts 107 (source and drain electrodes) through these slightly sticking out portions (that is, the upper planes and the sides of the source and drain semiconductor regions) to make the area of connection larger. Furthermore, the contacts 107 are extended over the upper portion of the anodically oxidized film 110, at which they are patterned into separate electrodes. In FIG. 5, a channel is located adjacent to the gate electrode 108 between the source and drain semiconductor regions 103 under a gate insulating film 106. In FIG. 5, the gate insulating film 106 is provided between the channel and the gate electrode 108. In FIG. 5, said anodically oxidized film 110 is provided between the gate electrode 108 and the source and drain electrodes 107.
Referring to FIG. 7, a fabrication process for the TFT according to an embodiment of the present invention and having the structure illustrated in FIG. 5 is explained. The FIG. 7 is provided as an explanatory means and the details concerning dimension and shape are a little different from those of the actual device.
First, as in FIG. 7(A), on a glass substrate, e. g., a substrate of a heat-resistant crystallized glass 101, is deposited a semiconductor layer 102. The semiconductor layer, e.g., a silicon semiconductor layer, may be an amorphous semiconductor, a polycrystalline semiconductor, or any other selected from a wide variation, and may be deposited by processes such as a plasma-assisted CVD (chemical vapor deposition), sputtering, and pyrolytic CVD, depending on the type of the semiconductor used. In the following explanation, the process steps are described according to a case in which a polycrystalline silicon semiconductor is used. The next step in the fabrication process comprises forming a silicon oxide film 106 on the semiconductor layer 102, so that the silicon oxide film 106 may function as the gate insulating film. Further on the silicon oxide film is formed an contact material layer, an aluminum layer in this case, from which a gate electrode is established. The contact material layer is then patterned into the gate electrode 108 using a first mask {circle around (21)}. An anodically oxidized film is provided as a surrounding of the gate electrode 108, by conducting an anodic oxidation in an electrolyte for the anodic oxidation. A pore-free aluminum oxide 110 can be provided at least at the vicinity of the channel region to the surrounding of the gate electrode, as illustrated in FIG. 7(B).
The electrolyte to be used in the anodic oxidation includes, representatively, strong acid solutions of, such as sulfuric acid, nitric acid, and phosphoric acid, as well as mixed acid comprising tartaric acid or citric acid, having added therein ethylene glycol or propylene glycol or the like. The solution (electrolyte) may be further mixed with a salt or an alkaline solution to adjust the solution (electrolyte) for the pH value.
The anodic oxidation was performed as follows. The substrate was immersed into an AGW electrolyte having prepared by adding 9 parts of propylene glycol to 1 part of an aqueous 3% tartaric acid solution. A direct current (D.C.) was applied to the substrate by connecting the aluminum gate to the anode of a power source and using a platinum cathode as the counter electrode. The electric current was applied first at a constant current density of 3 mA/cm2 for 20 minutes, and then at a constant voltage for 5 minutes, to thereby obtain a 1,500 xc3x85 thick aluminum oxide film around the gate electrode. The insulating properties of this aluminum oxide film was evaluated using a specimen having subjected to an oxidation treatment under the same condition as that employed above. As a result, a resistivity of 1015 xcexa9 and a dielectric breakdown of 3xc3x97106 V/cm was obtained for the film. The surface of the sample was observed through a scanning electron microscope to find surface irregularities at a magnification of about 10,000, but no minute holes. The film was therefore evaluated as a favorable insulator coating.
On the surface of the thus obtained insulator film was further deposited a silicon oxide film 112 by plasma-assisted CVD. The film was then anisotropically etched along a direction nearly vertical to the substrate to leave over silicon oxide 113 on the side walls of the protrusion constructed by the gate electrode and the anodically oxidized film (see FIG. 7(D)). The semiconductor layer 102 is then removed by etching in a self-aligned manner using the remaining silicon oxide film 113, and the gate electrode 108 and the anodically oxidized film 110 of the protrusion as a mask. The resulting structure is shown in FIG. 7(E). The structure as viewed from the upper side is shown in FIG. 8(A). The cross sectional view taken along the line A-Axe2x80x2 indicated in FIG. 8(A) is given in FIG. 7.
The structure as shown in FIG. 7(E) was subjected to a selective etching to remove only silicon oxide, i.e., the silicon oxide film 113 and the gate insulating film, using the gate electrode 108 and the anodically oxidized film 110 thereof as the mask, to thereby obtain a structure having a part of the semiconductor layer 102 exposed to outside at the edge of the gate, as shown in FIG. 7(F) and FIG. 8(B).
The resulting semiconductor portion exposed to the air is then doped with impurities to establish a source and a drain. As can be seen in FIG. 7(F), the part exposed to the air was bombarded with phosphorus ions from the upper side of the substrate using the anodically oxidized film 110 of the gate electrode as the mask. Thus are formed the source and drain regions 103. In FIG. 7(F), sides of the source and drain regions 103 are located at sides of the semiconductor portion exposed to the air. For the activation of the regions, a laser beam is irradiated to the exposed portions. Instead of carrying out the laser annealing as the activation treatment of the source and the drain regions, they can be otherwise activated by thermal annealing and the like.
An aluminum layer is then formed on the upper surface of the resulting structure, which is separated into source and drain electrodes by etching the aluminum layer into a predetermined pattern using a second mask {circle around (22)}. The structure obtained in this step is shown in FIG. 8(C). This structure is then finished into a TFT shown in FIGS. 7(G) and 8(D), by removing the unnecessary portions of the semiconductor layer 102 using the source and the drain electrodes 107 and the anodically oxidized film 110 on the gate electrode as the mask.
It can be seen from the foregoing description that the present invention provides a TFT by involving merely 2 masks.
In the case of a complementary TFT, 1 or 2 more masks suffice the fabrication of the structure.
The TFT thus obtained can be connected to the outer through a non-oxidized part of the gate electrode left out at the anodic oxidation, by carrying out the anodic oxidation treatment with care not to contact the part of the gate electrode with the electrolyte used at the anodic oxidation, or through a non-oxidized part of the gate electrode produced by selectively etching the anodically oxidized film exposed to the outer at the final step of selective etching of the source and drain electrodes together with the accompanying anodically oxidized film, after etching the unnecessary semiconductor layer. Otherwise, a contact hole may be perforated in a specific anodically oxidized film, using a third mask.
The foregoing description for the fabrication of a TFT is merely an example, and it should be understood that the present invention is not limited thereto. For example, the source and the drain regions may be doped with impurities by ion-bombardment at the stage shown in FIG. 7(B) using the anodically oxidized film 110 of the gate electrode as the mask, instead of carrying out the doping step after the patterning of the semiconductor layer 102 as demonstrated above in FIG. 7(F).
Furthermore, after the semiconductor layer 102 is established and before forming a gate, another photomask can be incorporated to carry out patterning of the semiconductor layer at the proximity of the TFT area into an island-like structure. Thus can be obtained a structure as shown in FIG. 9, which comprises only the substrate or an insulator film established on the substrate under the lead wiring instead of the semiconductor layer 102. Such a configuration avoids establishment of a capacitor which may otherwise be formed by the gate wiring and a semiconductor layer. In this manner can a TFT of an increased response be fabricated by using only 3 masks. The structure as viewed from the upper side is given in FIG. 9(A), and the cross sectional view along the line B-Bxe2x80x2 is given in FIG. 9(B).
In a general structure for an insulated gate field effect semiconductor device according to the present invention as shown in FIG. 5, the end of the gate is displaced from the position of the end of the source or the drain region by the thickness of the insulator film (anodically oxidized film) provided around the gate. Such an offset structure decreases the carrier density at the channel and, at the same time, reduces the electric field intensity at the drain-channel junction that the drain breakdown voltage can be improved. Since the thickness of the insulator film may be varied in the range of, for example, from 10 to 50 nm by changing the condition at the oxidation, the amount of this offset can be readily set as desired, depending on the required device characteristics. Furthermore, a lightly doped drain (LDD) structure can be realized by controlling the impurity concentration of this offset portion to a value lower than that in the source and the drain regions.
In FIG. 5, a channel length (a distance between the source and the drain regions) is longer than a length of the gate electrode in a direction of the channel length.
An offset region to which no electric field or very weak electric field is applied by a gate voltage can be formed in a portion of a channel region in contact with a source or a drain region in an insulated gate field effect transistor in which a channel length thereof is longer than a length of a gate electrode thereof in a direction of the channel length. For example, in FIG. 5, no electric field is applied to the offset region located in the channel region in the semiconductor 102 between a portion of the channel region just under the gate electrode 108 and the source or the drain region, a very weak electric field is applied to the offset region as compared with an electric field applied to the portion of the channel region just under the gate electrode 108. In FIG. 5, for example, the channel length is longer than the length of the gate electrode 108 in the direction of the channel length by an approximately twofold thickness of the insulator film (anodically oxidized film).